POSTING ACTIVE · REQ-F72BF · FY26.Q2

Principal PLL IC Design Engineer - TeraWave

Blue Origin
[ COMPANY ]
[ POSTED ]
[ REQ ID ]
[ COMPENSATION RANGE · ANNUAL · BASE ]
$269,175 – $376,844USD
MIDPOINT
$323,010
SPREAD
$107,669
LEVEL
SENIOR
TECHNICAL STACK · 1 TAGS
§ 01OVERVIEW

Application close date:

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! 

Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.

We are seeking a Principal IC Design Engineer to lead the development of integrated Phase-Locked Loops (PLLs) and clocking systems in advanced CMOS/SiGe processes. This role requires extensive design experience, particularly at mmWave frequencies, and is essential for advancing our technology offerings in space communication systems. You will be responsible for delivering state-of-the-art performance while contributing to innovative solutions that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth.
 

§ 02SPECIAL MENTIONS:

 - Relocation provided

 - Travel expected up to 10% of the time

 - Interviews will include a technical assessment

 - This role will be based onsite in either the San Diego, CA; Bay Area, CA; or Renton, WA. A temporary remote work exception is approved while our Bay Area and San Diego sites are being developed.
 

§ 03RESPONSIBILITIES INCLUDE BUT ARE NOT LIMITED TO:
  • Leading the design, development and integration of PLLs and clock distribution in advanced CMOS FinFET and SiGe technologies, focusing on performance optimization and trade-off analysis.
  • Utilizing full proficiency in Spectre and AMS flows to develop high-performance PLL circuits.
  • Collaborating with RF and SOC system architects to define requirements for PLLs and their sub-blocks based on system specifications, ensuring seamless integration into RF payloads and terminals.
  • Overseeing layout, top-level integration, floorplanning, and verification of the overall design for successful tape-out cycle.
  • Working closely with validation and product engineers to develop test plans, facilitate bring-up, optimize performance, and ensure reliable & high-yield production cycles.
  • Investigating and implementing fundamental analog building blocks to enhance overall circuit performance
  • Mentoring junior engineers for best design practices in analog domain.
     
§ 04MINIMUM QUALIFICATIONS:
  • Bachelor's degree in Electrical Engineering, or related technical discipline
  • 10+ years of experience in the design and development of high-speed (>20GHz) PLLs, and LO generation for high-performance applications at RF and mmWave frequencies
  • Proven expertise in loop design for phase noise/jitter, spur profile, area, and power optimization
  • Proficient in the design of PLLs and clock distribution circuits for wireless and wireline applications
  • Experience with clock domain synchronization techniques within systems involving multiple PLLs and/or clock domains
  • Fundamental understanding of device physics for process selection and performance optimization
  • Full proficiency in mixed-mode and RF modeling, simulation, and verification methodologies using toolsets such as MATLAB, Spectre, SystemVerilog, and AMS
  • Extensive experience in PLL silicon characterization and debugging
  • Proficiency in the design of fundamental analog/RF building blocks, including amplifiers, filters, mixers, harmonic-rejection mixers, pre-scalers, and frequency multipliers
  • Must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum
     
§ 05PREFERRED QUALIFICATIONS:
  • Advanced degree (MS/PhD) in Electrical Engineering or related field
  • Experience designing fractional-N PLLs, All-Digital PLLs (ADPLL) and/or sub-sampling PLLs is a plus
  • Extensive experience with fundamental analog building blocks such as LDOs, bias generators, and operational amplifiers
  • Familiarity with digital design, digital verification, and SystemVerilog modeling
§ 06SECTION

Base Pay Range for:

CA applicants is $269,175.00 - $376,843.95 WA applicants is $269,175.00 - $376,843.95
§ 07OTHER SITE RANGES MAY DIFFER
§ 08CULTURE STATEMENT

Don’t meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every desired qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles.

§ 09REQUIREMENTS

Description

  • Bachelor's degree in Electrical Engineering, or related technical discipline
  • 10+ years of experience in the design and development of high-speed (>20GHz) PLLs, and LO generation for high-performance applications at RF and mmWave frequencies
  • Proven expertise in loop design for phase noise/jitter, spur profile, area, and power optimization
  • Proficient in the design of PLLs and clock distribution circuits for wireless and wireline applications
  • Experience with clock domain synchronization techniques within systems involving multiple PLLs and/or clock domains
  • Fundamental understanding of device physics for process selection and performance optimization
  • Full proficiency in mixed-mode and RF modeling, simulation, and verification methodologies using toolsets such as MATLAB, Spectre, SystemVerilog, and AMS
  • Extensive experience in PLL silicon characterization and debugging
  • Proficiency in the design of fundamental analog/RF building blocks, including amplifiers, filters, mixers, harmonic-rejection mixers, pre-scalers, and frequency multipliers
  • Must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum
§ 10NICE TO HAVE

Base Pay Range for

CA applicants is $269,175.00 - $376,843.95 WA applicants is $269,175.00 - $376,843.95

Other site ranges may differ

Culture Statement

Don’t meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every desired qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles.

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