POSTING ACTIVE · REQ-25586 · FY26.Q3

Senior FPGA Design & Verification Engineer – TeraWave

Blue Origin
[ COMPANY ]
[ POSTED ]
[ REQ ID ]
[ COMPENSATION RANGE · ANNUAL · BASE ]
$156,802 – $219,522USD
MIDPOINT
$188,162
SPREAD
$62,720
LEVEL
SENIOR
TECHNICAL STACK · 1 TAGS
§ 01OVERVIEW

Application close date:

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! 

Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.
§ 02OVERVIEW

Blue Origin is seeking a Senior FPGA Design and Verification Engineer to develop the digital signal processing and physical layer implementation for theTerawavenext generationmodem. In this role, you will architect, design, implement, and verify FPGA-based modem and physical layer solutions that enable robust, high-reliability communications for our spacecraft and ground systems.

Using latest generation hardware and modern design methodologies, you will work across the full development lifecyclefrom architecture and algorithm mapping through implementation, verification, and hardware bring-upcollaborating closely with systems, DSP/communications, RF, and avionics engineering teams.

§ 03RESPONSIBILITIES
  • Architect and design FPGA implementations of modem and physical layer functions on a SoC FPGA platform.

  • Translate communications system and DSP algorithm requirements into efficient, resource-optimized RTL (VHDL/Verilog/SystemVerilog).

  • Develop and execute comprehensive verification strategies, including self-checking testbenches, constrained-random verification, and coverage-driven methodologies (e.g., UVM).

  • Perform timing closure, resource optimization, and design implementation for high-performance FPGA and system-on-chip (SoC) platforms.

  • Support integration and hardware bring-up, including lab testing, debug, and validation against system-level performance requirements.

  • Collaborate with DSP/communications engineers to co-design and optimize physical layer algorithms for fixed-point FPGA implementation.

  • Contribute to design reviews, documentation, and design-for-test/design-for-reliability practices consistent with aerospace-grade development.

  • Support radiation-tolerant and high-reliability design considerations for space-based applications.

§ 04MINIMUM QUALIFICATIONS
  • Bachelor's degree or above inElectricalEngineering,ComputerEngineering, or equivalent.

  • 7+ years of experience in FPGA design and verification.

  • Strong proficiency in RTL design using VHDL and/or Verilog/SystemVerilog.

  • Experience implementing DSP or communications/modem functions in FPGAs (e.g., modulation/demodulation, FEC, filtering, digitalfront-ends).

  • Proficiency with FPGA development toolchains (e.g., Xilinx/AMDorIntel/Altera) and simulation tools.

  • Experience with verification methodologies including self-checking testbenches and functional coverage.

  • Strong understanding of timing analysis, constraints, and timing closure.

§ 05PREFERRED QUALIFICATIONS
  • Background in digital communications theory and physical layer design (synchronization, equalization, carrier/timing recovery, link budgets).

  • Experience with system-on-chip (SoC) platforms integrating FPGA fabric and embedded processors.

  • Experience in embedded development in C/C++, or experience writing low level drivers.

  • Experience developing test venue software and hardware infrastructure for hardware-in-the-loop (HIL) testing environment.

§ 06SECTION

Base Pay Range for:

CA applicants is $156,802.00 - $219,522.45 WA applicants is $156,802.00 - $219,522.45
§ 07OTHER SITE RANGES MAY DIFFER

§ 08CULTURE STATEMENT

Don’t meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every desired qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles.


§ 09REQUIREMENTS

Description

  • Bachelor's degree or above in Electrical Engineering, Computer Engineering, or equivalent.
  • 7+ years of experience in FPGA design and verification.
  • Strong proficiency in RTL design using VHDL and/or Verilog/SystemVerilog.
  • Experience implementing DSP or communications/modem functions in FPGAs (e.g., modulation/demodulation, FEC, filtering, digital front-ends).
  • Proficiency with FPGA development toolchains (e.g., Xilinx/AMD or Intel/Altera) and simulation tools.
  • Experience with verification methodologies including self-checking testbenches and functional coverage.
  • Strong understanding of timing analysis, constraints, and timing closure.
QUESTIONS AND ANSWERS
How much does the Senior FPGA Design & Verification Engineer – TeraWave at Blue Origin pay?
The posting lists a range of $157K–$220K per year. Ranges reflect what Blue Origin publicly declared on the source posting.
Where is this Senior FPGA Design & Verification Engineer – TeraWave role based?
The role is based in Greater Seattle Area.
What experience does Blue Origin expect for this role?
The posting is tagged as a senior-level role, typically 5+ years of experience. Check the requirements section for specifics.
How was this posting sourced?
This role was pulled directly from Blue Origin's Workday careers site. Apply links open in the employer's own ATS — no reposts or aggregator middleware.
[ APPLICATION ROUTE ]WORKDAY · External ATS

Apply links open in the employer's official ATS. Always verify recruitment messages on the company's careers page before sharing personal information.

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